Method for producing a field-effect transistor, field-effect transistor and integrated circuit arrangement

ABSTRACT

A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

The invention relates, inter alia, to a method for producing a field-effect transistor, in particular a tunnel field-effect transistor. The following steps are carried out in the method, without any restriction by the order in which the method steps are listed:

-   -   providing a substrate, on which an auxiliary layer is arranged,     -   patterning the auxiliary layer by removing material of the         auxiliary layer, at least one auxiliary region being produced,     -   producing a first spacer element in a region in which material         of the auxiliary layer has been removed,     -   doping a first connection region of a field-effect transistor,         the first spacer element and the auxiliary region serving as a         mask, and     -   covering the first connection region with a covering material or         a covering layer.

The substrate is a monocrystalline semiconductor substrate, for example, in particular monocrystalline silicon. SOI substrates (silicon on insulator) are particularly suitable. The auxiliary layer comprises for example a different material than the substrate or the same material. Auxiliary layers composed of polycrystalline silicon are often used, from which gate electrodes of the transistor can be produced.

The spacer element is also referred to as a spacer and defines a distance between the connection region and a channel forming region in the substrate. The connection regions are usually also referred to as source/drain regions and can optionally contain so-called extension regions or extensions, for example so-called LDD zones (lightly doped drain), that is to say regions of the same doping type as the adjoining connection region but with a lower dopant concentration. When producing field-effect transistors having connection regions of the same doping type, the gate electrode or the auxiliary region and also the spacer elements serve as a mask when doping the first connection region.

On the other hand, there are, however, tunnel field-effect transistors in which the connection regions have mutually different doping types. In this case, when doping one connection region, the respective other connection region could be covered with a resist mask that is patterned with the aid of a photolithographic step in such a way that its edge lies on the auxiliary region. In this case, the doping of the connection region remains self-aligning despite the use of the resist.

It is an object of the invention to specify a simple method for producing a field-effect transistor, in particular a tunnel field-effect transistor, which makes it possible, in particular, to produce field-effect transistors having small lateral dimensions. Moreover, the intention is to specify a field-effect transistor and an integrated circuit arrangement.

The object relating to the method is achieved by means of a method having the method steps specified in patent claim 1. Developments are specified in the subclaims.

The invention is based on the consideration that it is possible to produce tunnel field-effect transistors having dimensions of less than 50 nm (nanometers) and in particular within the range of 15 nm to 30 nm, without short channel effects (SCE) occurring, which impair the electrical functional properties of the tunnel field-effect transistor.

Therefore, in the method according to the invention, the following method steps are carried out in addition to the method steps mentioned in the introduction:

-   -   removing material of the auxiliary region,     -   producing a second spacer element in a region in which material         of the auxiliary region has been removed, and     -   doping a second connection region of the field-effect         transistor, the second spacer element and the covering material         serving as a mask.

Accordingly, in the method according to the invention, the material of the auxiliary region is again removed completely or at the very least partially, such that the resultant space can be used for a spacer element. This makes it possible to produce field-effect transistors having very small lateral dimensions.

In the method according to the invention, the covering material or the covering layer is a layer that is planarized by means of a CMP method (chemical mechanical polishing), for example. The method according to the invention makes it possible to dope the connection regions without having to use a photolithographic step in which an edge of the photomask lies within the zone in which the transistor is to be produced. However, photomasks can be used in order to select, on the integrated circuit arrangement, regions in which a specific type of transistors is to be produced.

In one development of the method according to the invention, the auxiliary layer is firstly patterned by means of a photolithographic method, a projection having two sidewalls facing away from one another or a trench having two sidewalls facing one another arising. In a plane lying at an angle of 90 degrees with respect to a plane in which the substrate is arranged, the projection has for example a rectangular cross section or a trapezoidal cross section, sidewalls of the trapezoid being inclined symmetrically with respect to one another. In said plane, the trench likewise has a rectangular cross section or a trapezoidal cross section, in which case the trench width can decrease as the depth increases. In one configuration, the lateral dimension of the projection or of the trench is less than 500 nm, or less than 250 nm or even less than 100 nm. In this case, the lateral dimension is given, for example, by the smallest lateral feature size that can be achieved by the lithography method used.

In a next development of the method according to the invention, a control region of the field-effect transistor is produced after the removal of material of the auxiliary region or during the removal of material of the auxiliary region. The method steps performed in this case are explained in more detail below with reference to FIGS. 3 and 6.

In an alternative development, a control region of the field-effect transistor is produced before the production of the first spacer element on the projection or in the trench. Method steps performed in this case are explained in more detail below with reference to FIGS. 5 and 7.

Consequently, there are a large number of possibilities for carrying out the method according to the invention. One or other of said possibilities has particular technical effects depending on the other production steps required. The large number of possibilities enables more degrees of freedom in the production.

In a next development of the method, no extension regions, that is to say no LDD regions or so-called extensions, are produced on the connection regions or on the source/drain regions. In the case of tunnel field-effect transistors, a steep dopant concentration gradient brought about or promoted by the absence of the extension region at the tunnel junction promotes the commencement of the tunnel and hence a control effect that is as large as possible. In an alternative development, an extension region is produced on one connection region, but not on the other connection region, in particular not on the connection region at which tunneling occurs.

In a next development of the method, only one connection region is silicided. A siliciding on the other connection region is suppressed. By virtue of this measure, in the case of tunnel field-effect transistors it is likewise possible to achieve an improvement of the electrical properties of the transistor. The non-silicided connection region is, in particular, the connection region at which tunneling takes place.

The invention additionally relates to an integrated tunnel field-effect transistor containing the following elements:

-   -   a preferably semiconducting channel forming region, which is         undoped, i.e. intrinsically doped, or doped comparatively         lightly in comparison with other regions of the transistor. The         channel forming region is preferably formed in monocrystalline         material.     -   A preferably semiconducting first doped connection region         (source/drain region), which is doped in accordance with a first         doping type and with a greater dopant concentration than the         channel forming region.     -   A preferably semiconducting second doped connection region,         which is doped in accordance with a different doping type than         the first connection region and with a greater dopant         concentration than the channel forming region. By way of         example, the first connection region is heavily p-doped and the         second connection region is heavily n-doped. As an alternative,         the first connection region is heavily n-doped and the second         connection region is heavily p-doped. The dopant concentration         in the connection region at which tunneling is intended to occur         is, in particular, greater than 10¹⁹ or even greater than 10²⁰         dopant atoms per cm³. Moreover, the connection regions, and if         appropriate, the extension regions are preferably formed in a         monocrystalline material.     -   The channel forming region is arranged between the first         connection region and the second connection region.     -   A control region, also referred to as a gate.     -   An electrically insulating insulation region arranged between         the control region and the channel forming region.

The tunnel field-effect transistor according to the invention has a minimum lateral extent of the control region at the insulation region of less than 50 nm or even less than 30 nm. In particular, however, the lateral extent is greater than 5 nm or greater than 10 nm. The tunnel field-effect transistor according to the invention can be produced by the method according to the invention, for example, such that the technical effects mentioned above are applicable.

In one development of the field-effect transistor, the field-effect transistor has an asymmetrical construction, which has likewise been brought about for example by the use of the method according to the invention. In a next development, the asymmetry is manifested in the fact that the control region has a sidewall that lies vertically with respect to a plane in which the insulating layer lies. By contrast, a sidewall of the control region that faces away from said sidewall is convex, i.e. outwardly bulging. In the case of control regions having exclusively vertical sidewalls, the asymmetry arises, for example, by means of spacers of different heights on sides of the gate region that face away from one another.

The invention additionally relates to an integrated circuit arrangement containing at least two tunnel field-effect transistors according to the invention or, alongside at least one tunnel field-effect transistor according to the invention, also at least one further field-effect transistor which has connection regions of the same doping type but which for the rest has the same construction as the tunnel field-effect transistor according to the invention. The further field-effect transistor is therefore not a tunnel field-effect transistor. Furthermore, the integrated circuit arrangement can additionally also contain planar tunnel field-effect transistors in which the control regions have been patterned by a lithographic method rather than by a sublithographic method.

Exemplary embodiments of the invention are explained below with reference to the accompanying drawings, in which:

FIGS. 1 to 4 show production stages in the production of tunnel field-effect transistors in accordance with a first exemplary embodiment, in which a projection is produced at whose location gate regions are produced,

FIG. 5 shows a production stage in the production of a tunnel field-effect transistor in accordance with a second exemplary embodiment, in which a projection is produced at which gate regions are produced,

FIG. 6 shows a production stage in the production of a tunnel field-effect transistor in accordance with a third exemplary embodiment, in which a trench is produced in which no gate regions are produced, and

FIG. 7 shows a production stage in the production of a tunnel field-effect transistor in accordance with a fourth exemplary embodiment, in which a trench is produced in which gate regions are produced.

FIGS. 1 to 4 show production stages in the production of tunnel field-effect transistors T1 and T2 in accordance with a first exemplary embodiment. As is illustrated in FIG. 1, a monocrystalline semiconductor substrate 10, for example a silicon wafer, is taken as a starting point. The wafer surface is prepared, e.g. by cleaning Isolation zones between adjacent transistors are subsequently produced, for example by the use of the LOCOS method (LOCal Oxidation) or by the use of shallow isolation trenches. As is shown in FIG. 1, shallow isolation trenches 32, 34 and 36 can be produced for separation between individual transistors T1, T2 of the integrated circuit arrangement. The isolation trenches 32 to 36 have for example a depth of 200 nm or of greater than 200 nm. The isolation trenches 32 to 36 are filled with silicon dioxide, for example. The isolation trench 34, for example, also makes it possible to achieve, in all the exemplary embodiments, a separation of the drain/source regions lying between the transistors produced in pairs, see e.g., drain/source region for the transistors T1 and T2.

Channel implantations ensue, for example, by means of which, in particular, threshold voltages of the transistors are also predetermined. An insulating layer 12 is subsequently applied, which can be used as gate dielectric, for example by thermal oxidation.

After the application of the insulating layer 12, an auxiliary layer 14 is applied, for example composed of polycrystalline silicon. The thickness of the insulating layer 12 is for example only 2 nm (nanometers) or is less than 2 nm. The thickness of the auxiliary layer 14 is for example 50 nm or less. A resist is subsequently applied for example a photoresist. The resist is exposed and developed by means of a photolithographic method, a resist region 16 remaining which has a lateral extent L1 of for example 150 nm (nanometers) or less. The auxiliary layer 14 is patterned with the aid of the resist region, an auxiliary region 18 arising. The insulating layer 12 is also patterned at the same time or at a later point in time. During the patterning of the auxiliary layer 14, the process stops on the substrate 10 or on the insulating layer 12. Auxiliary regions 18 in other parts of the circuit arrangement are used for example as gate electrodes of planar CMOS field-effect transistors with connection regions having the same type of doping. The patterning of the auxiliary layer 14 is carried out for example by means of an anisotropic etching method, for example by means of an RIE method (Reactive Ion Etching). Optionally, a so-called trimming process can be carried out in which the lateral extent L1 of the auxiliary regions 18 is reduced further by means of an isotropic etching for example.

The process steps explained above are performed equally for all types of transistors on the integrated circuit arrangement, that is to say for transistors having a large gate length (i.e. larger than sublithographic), for CMOS transistors (Complementary Metal Oxide Semiconductor) having a sublithographic gate length, and for tunnel field-effect transistors. In other exemplary embodiments, however, the integrated circuit arrangement contains only one or more but not all of the types of transistors mentioned.

As is illustrated in FIG. 1, the auxiliary region 18 is laterally delimited by sidewalls 18 a and 18 b. The auxiliary region 18 is terminated toward the top by a top face 18 c. The bottom of the auxiliary region 18 lies on an insulating layer region 20.

As is further illustrated in FIG. 1, after the patterning of the auxiliary region 18, optional sidewall insulations are produced on the lateral faces 18 a and 18 b of said auxiliary region, for example sidewall oxides 22 and 23, for example by thermal oxidation. The sidewall insulations or sidewall oxides 22 and 23 are produced particularly on those transistors on which so-called extensions are required in order to provide one more degree of freedom. By way of example, the sidewall oxides can also eliminate damage to the gate oxide caused by the patterning of the gate oxide. By means of a subsequent implantation step, the extension regions 24 and 25 are produced using the sidewall oxides 22, 23 and the auxiliary region 18 as a mask.

After the production of the extension regions 24, or directly after the patterning of the auxiliary region 18, spacers 26, 27 are produced on the sides of the sidewall oxides or on the sides of the auxiliary region 18. For this purpose, a layer is deposited with a layer thickness corresponding to the later width of the spacers 26, 27. The spacers 26 and 27 are then produced by anisotropic etching back. By way of example, the spacers 26, 27 comprise silicon nitride. However, other materials are also possible.

After the production of the spacers 26, 27, source and drain implantations are carried out in order to produce drain/source regions 28, 29, a higher implantation energy and also a higher dose than when producing the extension regions 24, 25 being used. Resist masks can be used to select regions in which the drain/source regions are intended to be n-doped or other regions in which they are intended to p-doped. However, the implantation is effected in self-aligning fashion at the spacers 26, 27.

The method steps explained above can also be carried out equally for CMOS transistors having large gate lengths, for CMOS transistors having ultra short gate lengths and for tunnel transistors. In the exemplary embodiment, the width of the sidewall oxides 22, 23 is for example 5 nm (nanometers) or less. The width of the spacers 26, 27 is for example 10 nm or less.

As is furthermore illustrated in FIG. 1, after the implantation of the drain/source regions 28, 29, filling material 30 is deposited over the whole area and planarized, for example with the aid of a CMP method. The CMP method stops e.g. on the auxiliary region 18.

In the exemplary embodiment, BSG (BoroSilicate Glass), for example, is used as material of the filling layer 30. Other exemplary embodiments, however, use other materials for the filling layer 30 which can be etched in particular selectively with respect to polycrystalline silicon, with respect to silicon dioxide and with respect to silicon nitride.

As is illustrated in FIG. 2, regions in which CMOS transistors or tunnel transistors having ultra short gate lengths are intended to be produced are subsequently selected for example optionally with the aid of a photolithographic process. In these regions, the auxiliary region 18 is completely removed, etching being effected selectively with respect to the filling material 30 and with respect to the spacers 26, 27 or with respect to the sidewall oxide 22, 23. The insulating layer region 20 remains at the bottom of a cut-out 50, which arises where the auxiliary region 18 was arranged. If appropriate, however, the insulating layer region 20 can be produced anew by a thermal oxidation. The etch can take place as a selective wet etching process or as a selective dry etch. In the case of a wet etch, high selectivities are achieved e.g. by means of NaOH (sodium hydroxide) diluted in H₂O (water).

As is furthermore illustrated in FIG. 3, a layer composed of gate material is subsequently deposited, for example a polycrystalline layer. The thickness of said layer defines the width of gate regions 60, 62 which arise after an anisotropic etching-back process on the sidewalls of the cut-out 50. In the exemplary embodiment, the layer thickness is e.g. 20 nanometers. After the anisotropic etching-back process, a sidewall oxidation is optionally carried out in order to produce sidewall oxides 64 and 65 on the uncovered lateral faces of the gate regions 60, 62. As an alternative, first sidewall spacers 64, 65 are produced by layer deposition and anisotropic etching back. If extension regions 72, 73 are required, they are produced with the aid of a self-aligning implantation 70, the sidewall oxides 64, 65, the gate regions 60, 62 and the filling layer 30 serving as a mask. During the implantation, resist masks are optionally used, however, in order to define regions in which transistors that are intended to have n-type extension regions, for example, are located and regions in which transistors that are intended to have p-type extension regions are located.

As is furthermore illustrated in FIG. 3, spacers 74, 75 are subsequently produced on the sidewall oxides 64 and 65, respectively, or directly on the gate regions 60, 62, a layer deposition and an anisotropic etching-back step being used. The spacers 74 and 75 comprise silicon nitride, for example. Drain/source regions 80 are subsequently implanted, the spacers 74, 75, the gate regions 60, 62 and the filling layer 30 serving as a mask. The implantation is self-aligning within a transistor. With the aid of optional photolithographic processes, however, regions on the integrated circuit arrangement can be selected in which, by way of example, n+ source/drain implantations are intended to be carried out or in which, alternatively, p+ source/drain implantations are intended to take place.

As is further illustrated in FIG. 4, oxide on the gate regions 60, 62 is removed for example with the aid of a wet etch or with the aid of a dry etch. The filling layer 30, too, is optionally removed. With the aid of an optional known salicide method (self-aligned silicide), silicide regions 90, 92, 94, 96, 98 are subsequently produced on the drain/source regions 28, 29, on the gate regions 60, 62 and on the drain/source region 80. If the filling layer 30 remains, then contacts to the connection regions are introduced into the filling layer.

The formation of the silicide region 94 between the two spacers 74, 75 is suppressed in an alternative method implementation, for example by whole-area deposition and etching-back of an auxiliary layer. The selectivity of an etch is utilized as an alternative. The gate insulation is nitrided, for example, that is to say that it has a nitrogen-rich top face. Use is also made of gate insulation layer stacks in which a top silicon nitride layer is present. Silicon nitride has a different etching rate than oxide both during a wet etch and during a dry etch, so that the silicon oxide on the gate regions 60, 62 can be removed without removing the gate dielectric between the gate regions 60, 62. This means that no silicide can then be formed between the two gate regions 60 and 62.

In an alternative method implementation, so-called raised source/drain regions are produced by introducing another selective epitaxy, for example.

By means of an additional trimming process, using e.g. a lithographic method and/or a spacer technique, the gate regions 60 and 62 are separated from one another on the sides of the cut-out 50 which lie opposite one another and which are not illustrated in FIG. 4.

In another exemplary embodiment, a cover layer e.g. composed of silicon nitride is applied to the as yet unpatterned auxiliary layer 14. The cover layer and the auxiliary layer 14 are then patterned jointly, an auxiliary region being produced which corresponds to the auxiliary region 18 and which is completely covered by a region of the cover layer. The steps for producing optional sidewall oxides, optional extension regions, spacers and connection regions as explained with reference to FIG. 1 are then carried out. Prior to the application of a layer corresponding to the filling layer 30, the prepatterned cover layer region is etched back isotropically, so that edge regions of the auxiliary region corresponding to the auxiliary region 18 are uncovered, but the auxiliary region is still covered with the etched-back cover layer region in a central part. A similar etching-back process is explained below with reference to FIG. 6 for a cover layer 221. A layer corresponding to the filling layer 30 is then applied and planarized, the process stopping e.g. upon reaching the residual cover layer region. The filling layer then still covers the edge regions of the auxiliary region that were uncovered during the isotropic etching back. The cover layer region is then removed from the center of the auxiliary region selectively with respect to the material of the filling layer. The auxiliary region is subsequently patterned using the material of the planarized filling layer that covers the edge of the auxiliary region, no photomask being used. This patterning gives rise to regions which correspond to the gate regions 60 and 62 but which do not have rounded sidewalls but rather planar sidewalls which face one another. The steps for producing an optional sidewall oxide, optional extension regions, spacers and the connection region corresponding to the connection region 80 as explained with reference to FIG. 3 are then produced.

FIG. 5 shows a production stage in the production of transistors in accordance with a second exemplary embodiment. In the second exemplary embodiment, the same method steps as in the first exemplary embodiment for producing the same elements are carried out apart from the differences explained below. For differentiation, however, the elements of the second exemplary embodiment have reference symbols preceded by a 1 in comparison with identical elements of the first exemplary embodiment. By way of example, in the second exemplary embodiment a substrate 110 corresponds to the substrate 10. In the second exemplary embodiment, on an auxiliary region 118 corresponding to the auxiliary region 18, gate regions 160 and 162 are produced on the sidewalls before the spacers 126 and 127, respectively is produced. The material of the auxiliary region 118 is chosen such that it can be removed selectively with respect to the gate regions 160 and 162. By way of example, nitride is suitable as material for the auxiliary region 118. After the production of the spacers 126 and 127 a filling layer 130 composed of BSG (BoroSilicate Glass), for example, is applied. The method steps explained above with reference to FIGS. 2 to 4 are then performed, but after the removal of the auxiliary region 118, it is no longer necessary to produce gate regions within the cut-out that arises. If appropriate, only sidewall oxides and spacers are produced within the cut-out.

FIG. 6 shows a production stage in the production of transistors in accordance with a third exemplary embodiment. In contrast to the first exemplary embodiment and the second exemplary embodiment, however, the two transistors are not produced on a projection, but rather in a trench 222. Once again a silicon substrate 210 is taken as a starting point, on which an insulating layer 212, for example, is optionally deposited. An auxiliary layer 214, for example composed of polycrystalline silicon and having a layer thickness of 50 nm, for example, is applied to the insulating layer 212. A trench 222 having sidewalls 222 a and 222 b is subsequently produced with the aid of a photolithographic method. The trench 222 has a lateral extent L2, of 150 nm, for example. When producing the trench 222, the process stops on the insulating layer 212, so that the trench bottom is situated on the insulating layer 212. After the production of the trench 222, an auxiliary region 219 a arises on the left of the trench 222 and an auxiliary region 219 b arises on the right of the trench 222. Spacers 274 and 275 are produced on the sidewalls 222 a and 222 b with the aid of a layer deposition method and an anisotropic etching process. A source/drain region 280 is then produced with the aid of an implantation method, the spacers 274, 275 and also the auxiliary regions 219 a and 219 b serving as a mask. The trench 222 is subsequently filled with a filling material 290, for example with the aid of BSG (BoroSilicate Glass). Planarization is subsequently effected with the aid of a CMP method (Chemical Mechanical Polishing), e.g. as far as the upper end of the spacers 274, 275.

The auxiliary regions 219 a and 219 b are then completely removed. A gate region 294 is subsequently produced on the left of the spacer 274, e.g. by layer deposition and anisotropic etching back. Optionally, a sidewall oxide or sidewall spacer and a further spacer 226 can then be produced on the left of the gate region 294. Likewise, a gate region 296 is produced at the same time as the gate region 294 on the right of the spacer 275. A thermal sidewall oxide and a spacer 227, or two spacers, can be produced on the right of the gate region 296. An implantation for producing connection regions or drain/source regions 228, 229 is subsequently carried out, the outer spacers and also the filling region 290 serving as a mask. Extension regions are optionally implanted or doped prior to the production of the spacers 226, 227.

In an alternative method implementation, the auxiliary regions 219 a and 219 b are not completely removed, but rather only in regions outside gate regions 294 and 296. In this case, the following procedure can be adopted, by way of example:

-   -   a cover layer 221, for example composed of silicon nitride, is         deposited jointly with the auxiliary layer 214. The trench 222         also penetrates through the silicon nitride layer 221. After the         production of the spacers 274, 275 and the implantation 280, the         cover layer 221 is etched back isotropically, narrow regions at         the edges of the auxiliary regions 219 a and 219 b also being         uncovered. Afterward, as explained above, the filling material         290 is introduced and planarized, see line 292, the filling         material 290 also projecting somewhat over the auxiliary regions         219 a and 219 b. The projecting regions are used as a hard mask         for patterning the regions 219 a and 219 b during the production         of the gate regions 294 and 296, the auxiliary regions 219 a and         219 b only being partially removed, however. Further processing         is subsequently effected as explained above, that is to say,         inter alia, production of spacers 226, 227 and of connection         regions 228, 229.

FIG. 7 shows a production stage in the production of transistors in accordance with a fourth exemplary embodiment. The fourth exemplary embodiment involves carrying out method steps similar to those in the third exemplary embodiment; in particular, a trench 322 is produced. However, in the trench 322, before the production of sidewall spacers 374, 375, gate regions 394, 396 are produced, for example composed of polycrystalline silicon and by means of layer deposition and anisotropic etching back. After the production of spacers 374 and 375 in the trench 322, the trench 322 is filled with a filling material 390.

In the exemplary embodiment explained with reference to FIG. 7, an insulating layer 400, for example a silicon dioxide layer, is produced on the surface of the substrate and in particular also in the trench 322, by means of thermal oxidation. Consequently, an insulating layer 212 does not need to be applied in the exemplary embodiment explained with reference to FIG. 7. This makes it possible to produce the auxiliary regions 319 a and 319 b in a monocrystalline substrate as well, see dashed line 410. An auxiliary layer 311 formed by the auxiliary regions 319 a and 319 b therefore comprises monocrystalline silicon. However, in another exemplary embodiment, an insulating layer corresponding to the insulating layer 212 is used, on which an auxiliary layer 311 is then deposited.

As also in the third exemplary embodiment, a first alternative, in the fourth exemplary embodiment, the auxiliary regions 319 a and 319 b are completely removed after the introduction of the filling material 390 and planarization. Sidewall oxides or further spacers 326, 327 can be produced on the uncovered sides of the gate regions 394 and 396. After the production of the sidewall oxides or the further spacers 326, 327, the optional extension regions or source/drain regions 328, 329 are produced with the aid of an implantation, the sidewall oxides or the outer spacers 326, 327 and the filling material 390 serving as a mask.

A siliciding or a selective siliciding, see FIG. 4, can also be carried out in the exemplary embodiments explained with reference to FIGS. 5 to 7.

In all the exemplary embodiments, CMOS transistors having short gate lengths and tunnel field-effect transistors having short gate lengths can be produced in the manner explained. An additional trimming mask and an additional trimming process serve for removing gate regions or spacer regions that are not required, in particular gate regions that would connect different transistors T1 and T2. By means of an additional optional step, moreover, widened connection areas in comparison with the gate regions can be produced for the gate regions.

The methods specified therefore make it possible to produce tunnel field-effect transistors without lithographic alignment problems by means of a self-aligning formation of drain and source regions. To summarize, it holds true that the miniaturization of standard CMOS transistors has encountered its physical limits. Miniaturization brings about a deterioration in the electrical properties and an increase in the leakage currents. These limitations can be avoided by the use of tunnel field-effect transistors in which further miniaturizations are possible without short channel effects and without higher leakage currents. In particular n-channel tunnel field-effect transistors with an n-doped drain and a p-doped source or substrate are suitable.

The tunnel field-effect transistors contain a pin diode that is controlled with the aid of a gate isolated from the channel forming region by an insulation region. Instead of an intrinsic region, it is also possible to use a weakly n-doped, i.e. n⁻-doped, or a weakly p-doped, i.e. p⁻-doped, region. An electron channel or a hole channel is formed by the application of a voltage to the gate electrode. If the charge carrier concentration in the channel reaches degeneration, a tunnel junction arises on the source side of the channel, which enables a large transistor current. Although the pn junction is reverse-biased, a current flow emerges on account of the tunnel. The methods specified are suitable in particular below the 90 nm node for tunnel field-effect transistors having lengths within the range of 20 nm to 30 nm.

In contrast to methods in which tunnel field-effect transistors would be produced with a resist on a gate region in order to produce source and drain with different doping types, the methods explained above do not exhibit any alignment problems with regard to a resist edge. The method specified here avoids the difficulty of having to position the resist mask for the connection implantation precisely on a gate region, and therefore of requiring very large gate lengths. Moreover, CMOS transistors and tunnel transistors can be produced simultaneously.

In other exemplary embodiments, additional layers are also deposited between the layers explained with reference to FIGS. 1 to 7. This is not absolutely necessary, however, so that the abovementioned layer sequences between which no further layers are situated can also be deposited. 

1. An integrated circuit comprising: a first channel forming region that is undoped or doped disposed in a substrate; a first doped connection region that is doped in accordance with a first doping type and with a greater dopant concentration than the first channel forming region, the first doped connection region being disposed adjacent the first channel forming region; a second doped connection region that is doped in accordance with a second doping type that is different than the first doping type, the second doped connection region having a greater dopant concentration than the first channel forming region, the second doped connection region being disposed adjacent the first channel forming region, wherein the first channel forming region is disposed between the first doped connection region and the second doped connection region; a first control region, wherein the first control region comprises a first sidewall and an opposite second sidewall, and wherein the first sidewall is a planar surface and the second sidewall is a non-planar surface; an electrically insulating first insulation region arranged between the first control region and the first channel forming region, the first channel forming region, the first and the second doped connection regions, the first control region, and the electrically insulating first insulation region forming a first tunnel field effect transistor; a second channel forming region that is undoped or doped; a third doped connection region that is doped in accordance with the first doping type and with a greater dopant concentration than the second channel forming region; a fourth doped connection region that is doped in accordance with the second doping type the fourth doped connection region having a greater dopant concentration than the second channel forming region, wherein the second channel forming region is disposed between the third doped connection region and the fourth doped connection region; a second control region, wherein the second control region comprises a third sidewall and an opposite fourth sidewall, and wherein the third sidewall is a planar surface and the fourth sidewall is a non-planar surface; and an electrically insulating second insulation region arranged between the second control region and the second channel forming region, wherein the second channel forming region, the third and the fourth doped connection regions, the second control region, and the electrically insulating second insulation region form a second tunnel field effect transistor disposed on the substrate with the first tunnel field effect transistor.
 2. The integrated circuit of claim 1, wherein the critical dimension of the first control region on the first insulation region is greater than 5 nm but not greater than 30 nm.
 3. The integrated circuit of claim 1, wherein the first and second doped connection regions are part of a first tunnel field effect transistor that has a physically asymmetrical construction.
 4. The integrated circuit of claim 3, wherein the second sidewall comprises an asymmetrical control region having a convex sidewall facing away from said first sidewall.
 5. The integrated circuit of claim 3, wherein the first sidewall lies vertically with respect to a plane in which the insulation is arranged.
 6. The integrated circuit of claim 1, wherein a critical dimension of the second control region on the second insulation region is greater than 5 nm but not greater than 50 nm.
 7. The integrated circuit of claim 6, wherein the first channel forming region and the second channel forming region is located in a trench.
 8. The integrated circuit of claim 7, wherein the second and the fourth sidewalls of the first and the second control regions comprise asymmetrical control regions having convex sidewalls and wherein the convex sidewall face towards each other.
 9. The integrated circuit of claim 8, wherein spacers are arranged on the first and the second control regions and wherein the spacers have a convex sidewall facing away from the first and the second control regions.
 10. The integrated circuit of claim 6, wherein the second and the fourth sidewalls of the first and the second control regions comprise asymmetrical control regions having convex sidewalls and wherein the convex sidewall face away from each other.
 11. The integrated circuit of claim 1, wherein the first tunnel field effect transistor and the second tunnel field effect transistor are symmetrical with respect to a mirror plane lying between the first and second tunnel field effect transistors.
 12. The integrated circuit of claim 11, wherein mutually adjacent edges of the first control region and the second control region are spaced by a lateral distance that is not greater than 200 nm.
 13. The integrated circuit of claim 11, wherein mutually adjacent edges of the first control region and the second control region are spaced by a lateral distance that is not greater than 100 nm.
 14. The integrated circuit of claim 11, wherein mutually adjacent edges of the first control region and the second control region are spaced by a lateral distance that is not greater than 50 nm.
 15. The integrated circuit of claim 1, wherein the first channel forming region is located in a trench.
 16. The integrated circuit of claim 15, wherein the first control region comprises an asymmetrical control region having a convex sidewall facing away from the first sidewall.
 17. The integrated circuit of claim 16, wherein a spacer is arranged on the first control region and wherein the spacer has a convex sidewall facing away from the first control region.
 18. The integrated circuit of claim 1, wherein the first control region has a sidewall that lies vertically with respect to a plane in which the insulation is arranged and wherein the first control region is symmetric.
 19. The integrated circuit of claim 1, wherein the critical dimension of the first control region on the insulation region is greater than 5 nm but not greater than 50 nm.
 20. The integrated circuit of claim 1, further comprising a first silicide region disposed over and contacting a portion of the second sidewall.
 21. A semiconductor device comprising: a first channel region disposed in a semiconductor substrate; a first source extension region having a first doping type and with a greater dopant concentration than the first channel region; a first drain extension region having a second doping type that is opposite to the first doping type, the first drain extension region having a greater dopant concentration than the first channel region, wherein the first channel region is disposed between the first source extension region and the first drain extension region; a first gate region disposed above the first channel region, wherein the first gate region comprises a first sidewall and an opposite second sidewall, and wherein the first sidewall is a planar surface and the second sidewall is a non-planar surface; a first gate dielectric region arranged between the first gate region and the first channel region, the first channel region, the first source extension region, the first drain extension region, the first gate region, and the first gate dielectric region form a first tunnel field effect transistor; a second channel region disposed in the semiconductor substrate; a second source extension region having the first doping type and with a greater dopant concentration than the second channel region; a second drain extension region having the second doping type, the second drain extension region having a greater dopant concentration than the second channel region, wherein the second channel region is disposed between the second source extension region and the second drain extension region; a second gate region disposed above the second channel region, wherein the second gate region comprises a third sidewall and an opposite fourth sidewall, and wherein the third sidewall is a planar surface and the fourth sidewall is a non-planar surface; and a second gate dielectric region arranged between the second gate region and the second channel region, the second channel region, the second source extension region, the second drain extension region, the second gate region, and the second gate dielectric region form a second tunnel field effect transistor.
 22. The device of claim 21, wherein a gate length of the first gate region is greater than 5 nm but not greater than 50 nm.
 23. The device of claim 21, wherein the first tunnel field effect transistor has a physically asymmetrical construction.
 24. The device of claim 23, wherein the first gate region comprises an asymmetrical gate region, and wherein the second sidewall has a convex shape facing away from said first sidewall.
 25. The device of claim 21, wherein the first and the second source extension regions are coupled together through a doped region of the first doping type.
 26. The device of claim 25, wherein the first tunnel field effect transistor and the second tunnel field effect transistor are symmetrical with respect to a mirror plane lying between the first and second tunnel field effect transistors.
 27. The device of claim 25, wherein the mirror plane passes through the doped region coupling the first and the second source extension regions.
 28. A semiconductor device comprising: a first channel region disposed in a semiconductor substrate; a first source extension region having a first doping type and with a greater dopant concentration than the first channel region; a first drain extension region, the first drain extension region having a greater dopant concentration than the first channel region, wherein the first channel region is disposed between the first source extension region and the first drain extension region; a first gate region disposed above the first channel region, wherein the first gate region comprises a first sidewall and an opposite second sidewall, and wherein the first sidewall is a planar surface and the second sidewall is a non-planar surface; and a first gate dielectric region arranged between the first gate region and the first channel region, the first channel region, the first source extension region, the first drain extension region, the first gate region, and the first gate dielectric region form a first tunnel field effect transistor; a second channel region disposed in the semiconductor substrate; a second source extension region having the first doping type and with a greater dopant concentration than the second channel region; a second drain extension region, the second drain extension region having a greater dopant concentration than the second channel region, wherein the second channel region is disposed between the second source extension region and the second drain extension region; a shared source/drain region, wherein the shared source/drain region contacts the first and the second drain extension regions; a second gate region disposed above the second channel region, wherein the second gate region comprises a third sidewall and an opposite fourth sidewall, and wherein the third sidewall is a planar surface and the fourth sidewall is a non-planar surface; and a second gate dielectric region arranged between the second gate region and the second channel region, the second channel region, the second source extension region, the second drain extension region, the second gate region, and the second gate dielectric region form a second tunnel field effect transistor.
 29. The semiconductor device of claim 28, wherein the first drain extension region is a second doping type that is opposite to the first doping type, and wherein the second drain extension region has the second doping type.
 30. The semiconductor device of claim 29, further comprising: a first silicide region disposed over and contacting a portion of the second sidewall; a second silicide region disposed over and contacting a portion of the fourth sidewall; and a third silicide region disposed over and contacting a portion of the shared source/drain region.
 31. The semiconductor device of claim 29, wherein the critical dimension of the first gate region is greater than 5 nm but not greater than 50 nm. 